1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same. More specifically, the present invention relates to a semiconductor device having a trench-type device isolation region and a manufacturing method of the device isolation region.
2. Description of the Related Art
With the advance of microminiaturization (fine structuring) of integrated circuits, the area allowed for device isolation regions has been increasingly reduced. Thus, these conventional device isolation regions formed by means of LOCOS (Local Oxidation Of Silicon) are becoming difficult to use. To accommodate the recent fine structuring integrated circuits, trench device isolation has been proposed (for instance, see IBM Technical Disclosure Bulletin, Vol. 25, No. 8, Jan. 1983). However, if a MOS transistor is formed in a fine region surrounded with a device isolation region formed by this method, a new problem will arise in the properties of the resultant transistor.
First, the structure of a MOS transistor formed surrounded with a trench isolation region will be described with reference to FIGS. 1A, 1B and 1C. FIG. 1A is a plan view of the MOS transistor formed surrounded with the trench isolation region, and FIGS. 1B and 1C are cross-sectional views taken along the line 1B--1B and the line 1C--1C of FIG. 1A. For example, an n-type well 102 is formed surrounded with a trench isolation region 103 in a p-type silicon substrate 101. The trench isolation region 103 is formed of an insulating layer 107 deposited on the wall of a trench 109 and an insulating layer 108a embedded in the trench. A gate insulating layer 104 is deposited over the entire surface of the substrate 101 and a gate electrode 105 is then formed on a selected portion of the gate insulating layer. The gate electrode is formed so that both of its ends which are opposed to each other in the direction of its length overlap the isolation region 103. On the opposite sides of the gate electrode along its width, substrate regions surrounded with the isolation region 103 and the gate electrode 105 are ion implanted with impurities, such as phosphorus (P), arsenic (As) or the like, forming n-type diffused layers 106 which serve as the source and drain regions of the MOS transistor.
Next, the formation of the trench performed prior to the formation of that transistor and its associated problems will be described with reference to FIGS. 2A, 2B, and 2C. The formation of the well is omitted only for the purpose of simplifying the description. First, a thin layer 112 of silicon oxide of about 100 nm thickness is formed or deposited on the entire surface of the silicon substrate 101 by a conventional thermal oxidation technique. Then, the oxide layer 112 is coated with a photoresist layer and a resist pattern 113 is formed by the use of a lithography technique. Next, the oxide layer 112 is selectively etched with the resist pattern 113 used as a mask. After that, the silicon substrate 101 is etched to a depth of about 500 nm, forming the trench 109 for subsequent use as the device isolation region (FIG. 2A).
Next, after the removal of the resist pattern 113, an oxide layer 107 is thermally grown at a thickness of about 20 nm over the entire surface of the substrate including the trench 109 in order to remove etching induced damage. Then, an oxide layer 108 is deposited over the entire surface to a thickness of 1 .mu.m, whereby the trench is filled with the oxide layer 108 (FIG. 2B).
The oxide layer 108 is etched back by means of anisotropic etching or polishing, thereby leaving only a portion 108a of the oxide layer 108 in the trench 109. Subsequently, an ion implantation step (not shown) is performed for controlling the threshold voltages of MOSFETs. A gate oxide layer 104 is thermally grown to a thickness of about 10 nm and the gate electrode layer 105 of polycrystalline silicon is formed to a thickness of 300 nm (FIG. 2C). This figure corresponds to the case where the gate electrode layer 105 extends continuously over one trench portion in FIG. 1C.
In forming such a trench isolation region 103 it is required to allow for process margins for the etchback of the oxide layer 108. Thus, a predetermined amount of overetching is needed. As a result, the surface of the oxide layer 108a after the etching will become slightly lower than the surface of the silicon substrate 101. Thus, the gate oxide layer 104 will have nearly rectangular steps in the areas surrounded by circles A in FIG. 2C.
With such trench device isolation, an electric field is set up by a difference in level between the surface of the oxide layer 108a and the surface of the silicon substrate 101, which results in a decrease in the threshold voltage of the MOSFET. In a MOSFET with a narrow gate in particular, the electric field is enhanced in the step (edge) portions, which results in a significant decrease in the threshold voltage. This is due to a phenomenon by which a parasitic MOSFET having a low threshold voltage is formed in the edge portions where there is a difference in level between the substrate surface and the trench surface. This phenomenon is not desirable for MOS integrated circuits in which a very large number of MOSFETs having different gate widths are packed because the threshold voltage may vary from FET to FET. With the MOSFETs exhibiting this phenomenon there are the possibilities of an increase in standby current and a decrease in reliability of transistors; thus, it is desirable that this phenomenon should be eliminated.